The present invention relates generally to integrated circuits and their fabrication, and in particular, to a device with selective spacer formation on a first type of conductive material and local silicide interconnect formation on a second type of conductive material.
The use of a polysilicon layer for local interconnect has been reported in the literature for both bipolar and field effect (otherwise known as metal oxide semiconductor or "MOS") technologies. In bipolar processes, a polysilicon layer can be used to electrically contact base, collector, and emitter regions of bipolar transistors. In MOS technologies, a polysilicon layer can be used to electrically contact the source-drain regions of the MOS transistors and form the gates of MOS transistors. By suitable patterning of the polysilicon layer forming the buried contacts, a local interconnect may be formed. Global interconnects are then formed by contacting the polysilicon layer using conventional metal interconnects.
Since the number of metal layers which may be formed on a given portion of a wafer is limited, the use of a polysilicon layer for local interconnect allows a metal layer that was formerly used for local interconnect to be employed as an additional global interconnect layer. In addition to the advantages in layout provided by an additional global interconnect layer, the use of a polysilicon layer to form device contacts also results in an improvement in transistor performance through reduction in device parasitic areas (e.g., the extrinsic base area in bipolar transistors). It also results in simplification of contact etch technology for shallow junctions where very high etch selectivity to the substrate is required. This is particularly important in processes where dielectric planarization is performed before contact etch, because the thickness nonuniformity of the dielectric creates a substantial risk of etching into the shallow junction. By using a polysilicon layer to contact the shallow junction, metal contacts may be made to the polysilicon layer rather than the shallow junction, and the risk of overetching is reduced.
Recent processes also provide for fabricating metal silicide layers on desired components of bipolar circuits by a process that is self-aligned to the components. These processes have been modified to limit dopant movement from polysilicon into the silicide, to eliminate metallic contaminants from the surface of the field oxide surrounding active device areas, and to eliminate the need for masking/etching the metal silicide. One process utilizing some of the above techniques is taught by Koh et al. in U.S. Pat. No. 4,609,568.
Advanced complementary MOS (CMOS), bipolar/CMOS (BiCMOS), MOS, and bipolar devices have very high packing densities. The formation of spacers on the sidewalls of, for example, emitter/gate polysilicon regions on a substrate are essential in order to isolate these regions. Some processes form spacers on the sidewalls of the emitter/gate polysilicon patterns by depositing a uniform oxide where vertical polysilicon sidewalls have been created. A plasma etch is then performed to selectively remove oxide from horizontal surfaces of the polysilicon, but not the vertical sidewalls. This step may be followed by formation of metal silicide contacts.
While meeting with some success, the above processes have met with certain limitations. For example, contact resistance is often increased because only the top portion of the polysilicon is provided with a silicide region.
From the above, it is seen that an improved device with sidewall spacers and a method of fabrication thereof is desired.